P
PHATCAT
Technologies / EST. 2026
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EOL FPGA & CPLD Adapter Engineering

Keep your obsolete
fabric alive.

PhatCat Technologies designs and builds adapter and daughter-board packages that drop end-of-life FPGAs, CPLDs, and PLDs into modern programmable logic — same footprint, same function, HDL re-synthesis included. Ship tomorrow's silicon on yesterday's board.

200+
EOL FPGAs/CPLDs Mapped
8-12wk
Typical Turn
0
PCB Redesigns
REF / PC-ADP-001
PIN MAP
1:1 ACTIVE
LEGACY IN
TQFP-100
TARGET OUT
BGA-144
MODERN FPGA BGA-144 60.00mm
▸ SUPPORTED  XC9572XL  ◆  EPM7128S  ◆  SPARTAN-3  ◆  CYCLONE II  ◆  LC4128  ◆  ProASIC3  ◆  ATF1508AS  ◆  VIRTEX-II  ◆  MAX 7000  ◆  ispMACH 4000  ◆  FLEX 10K  ◆  XC95288  ◆  COOLRUNNER-II  ◆  CUSTOM REQUESTS ACCEPTED  ◆  
/ 01 — The Problem

When your fabric dies, production dies with it.

EOL notices on FPGAs and CPLDs cascade through supply chains in weeks. Counterfeit Spartans flood the brokers. Quartus II and ISE stop booting on modern OSes. The alternative — re-synthesizing to a new fabric and redesigning a qualified PCB — can cost more than the product itself and restart every certification on the line.

✕ PAIN — 01

Obsolete FPGA,
still in service.

Your industrial controller ships on a Spartan-3 that Xilinx killed in 2020. Gray-market stock is drying up and what's left has a known counterfeit problem — and the Xilinx ISE you'd need to reprogram it won't run on anything newer than Windows 10.

✕ PAIN — 02

Re-synthesis is
a nuclear option.

Retargeting to a new FPGA family means new toolchain licenses, new timing closure, new static timing analysis sign-off, new IP core licensing — then new PCB, new FCC filings, and requalification. An 18-month, seven-figure detour.

✕ PAIN — 03

Modern FPGAs
won't just drop in.

Your replacement runs at 1.2V core, 2.5V I/O. Yours ran at 3.3V. Your original was a TQFP-144. The replacement is a BGA-256 with different bank layout. You need a translator and a re-synthesis, not a substitute.

/ 02 — The Solution

We build the bridge between old and new.

A PhatCat adapter is a purpose-engineered daughter board that mounts where your EOL FPGA or CPLD used to sit and hosts a modern equivalent underneath. Voltage translation, bank remapping, config flash, and HDL porting to the new fabric are all handled in the package.

PC-ADP / CROSS-SECTION REV. 1.2
HOST PCB (UNCHANGED) PHATCAT ADAPTER — PC-ADP-001 I/O XLTR PWR TREE CFG FLASH MODERN FPGA BGA · 1.2V CORE ① Drops onto original PCB ② Hosts modern programmable logic ③ Level translation & interface conditioning onboard
01 /

Footprint-compatible

Pin mapping, mechanical height, and keepout zones match the original FPGA/CPLD package so your pick-and-place, your BOM, and your board all stay exactly as they are.

02 /

Electrically transparent

Onboard I/O voltage translators, multi-rail power tree, and reference-clock conditioning handle every electrical difference between legacy and modern silicon. Your board sees the original behavior.

03 /

HDL conversion: your team or ours

We recommend your engineers handle RTL re-synthesis and timing analysis against the modern FPGA we select — they know the design best. If resources aren't available, we'll do it as NRE, given your RTL source, timing constraints, pinout map, and interface description (signal levels, drive strength, loads).

04 /

Certification-preserving

Because the host PCB is untouched, most mechanical, EMC, and regulatory filings carry forward unchanged. We provide the documentation package to support your re-qualification delta.

/ 03 — Catalog

Starting with the programmable logic everyone still needs.

We're launching with adapters for the most widely deployed EOL programmable logic — the PLDs, CPLDs, and FPGAs that still drive 15-to-30-year-old industrial, aerospace, medical, and defense hardware. A standard adapter isn't always possible — package size, I/O count, and I/O type (input, output, bidirectional, voltage) determine feasibility on a case-by-case basis. If yours isn't listed, send it to us; custom work is the rest of what we do.

XC9572XL
Xilinx · XC9500XL CPLD

The industry-standard 72-macrocell CPLD deployed in millions of industrial boards. Adapter hosts modern CoolRunner-II-class fabric in the original TQFP-44/VQ44 footprint.

In Stock → View Details
EPM7128S
Altera · MAX 7000S CPLD

Altera's 128-macrocell 5V CPLD workhorse in PLCC-84 and TQFP-100. Our adapter preserves the original pinout with modern flash logic underneath.

In Stock → View Details
Spartan-3 XC3S400
Xilinx · FPGA (400K gates)

The most-deployed EOL low-cost FPGA in industrial control. Adapter hosts a modern Artix-7-class FPGA with bitstream porting included.

In Stock → View Details
Cyclone II EP2C8
Altera · FPGA (8,256 LEs)

Altera's Cyclone II — a staple of 2006-2015 industrial designs. Our adapter drops in modern Cyclone 10 silicon with HDL re-synthesis as part of the package.

In Stock → View Details
LC4128
Lattice · ispMACH 4000 CPLD

Lattice's 128-macrocell in-system programmable CPLD. Adapter hosts current-generation Lattice MachXO silicon with JTAG programming preserved.

In Development → Pre-order
ProASIC3 A3P250
Actel / Microsemi · Flash FPGA

The aerospace and defense favorite — flash-based, single-event-upset resilient. Replacement preserves flash boot behavior and SEU immunity.

In Development → Pre-order
ATF1508AS
Atmel / Microchip · CPLD

Atmel's 128-macrocell 5V CPLD in PLCC-84 and TQFP-100. Common in industrial I/O boards. Pin-compatible adapter in development.

In Development → Pre-order
Virtex-II XC2V1000
Xilinx · FPGA (1M gates)

Defense and industrial legacy — many flight systems still ship on Virtex-II. Adapter re-synthesizes to modern 7-series fabric.

In Development → Pre-order
+ Your FPGA Here
Custom Engineering Service

Have an EOL CPLD or FPGA killing your production? Send us the part number, quantity, and (if available) the HDL source. We'll scope feasibility in 5 business days.

Custom → Start Intake
/ 04 — Intake

What we need to start building.

Every adapter project begins with a short intake questionnaire. It tells us what your FPGA interfaces to — so we configure the onboard level translation, drive strength, and I/O topology to match your system exactly. Send us the information below and we'll come back in 5 business days with a firm feasibility assessment and quote.

/ 01 — Basics

Project basics

  • EOL part number and variant (e.g., XC3S400-4TQG144C)
  • Annual production volume and service horizon
  • Application and industry context
  • Target timeline and urgency
/ 02 — Interface

Hardware interface

  • Original package and pin count
  • Number and type of I/O pins (input, output, bidirectional)
  • I/O voltage domains per pin group
  • Drive strength and signal loading per I/O
  • Clocking topology (external XTAL, onboard PLL, etc.)
/ 03 — Design source

HDL & bitstream

  • RTL source (Verilog, VHDL, AHDL) if available
  • Original timing constraints (SDC, UCF, QSF)
  • Current pinout map and assignment
  • Bitstream (.bit, .pof, .sof, .jed) if source is lost
  • Encryption status — flag at intake
/ 04 — Context

Regulatory & logistics

  • Certification regime (FDA, DO-254, AS9100, AEC-Q, etc.)
  • Temperature grade (commercial, industrial, extended)
  • Country-of-origin requirements
  • NDA status before intake begins
Path A — your team handles HDL

Fastest and most economical. We specify the target FPGA and deliver the adapter hardware; your engineers re-synthesize against the new fabric. Sections 01 and 02 above are required at intake; 03 is optional.

Path B — we handle HDL on NRE

For teams without FPGA engineering bandwidth. We port the design ourselves as fixed-fee NRE. All four sections above are required — especially 03, which lets us scope the re-synthesis work accurately.

/ 05 — Process

From dead chip to shipping product.

Every engagement follows the same four stages. You stay in the loop at each gate and we never move forward without your sign-off.

01

Intake

You send the part number, datasheet, board context, and volume. We confirm feasibility within 5 business days and issue a fixed-fee engineering quote.

02

Design

Our engineers select a modern replacement FPGA, produce the pin-map, and lay out the adapter. You receive a proposal with the target silicon, adapter topology, and test plan for review.

03

Prototype

We fab, assemble, and bench-qualify the first articles against the original chip's spec envelope. You get prototypes, test data, and a signed conformance report.

04

Supply

Production adapters ship on your schedule with full traceability. Component sourcing, assembly, and inventory buffering are handled as a managed service.

/ 06 — Industries

Where our adapters keep products shipping.

Long-lifecycle industries with high certification costs are where EOL semiconductor replacement delivers the clearest ROI. These are the sectors we serve first.

Aerospace & Defense

25-year program lifecycles, DO-254 and MIL-STD-compliant supply chains, and parts that must outlast their fabs. Managed-supply programs with full lot traceability.

Medical Devices

FDA-cleared products where a component change triggers full revalidation. Adapters preserve the original BOM and keep 510(k) filings stable.

Industrial Control

PLCs, motor drives, HMI panels, and factory automation gear running on MCUs the vendors stopped making a decade ago. Our sweet spot.

Automotive & Transportation

Infotainment, telematics, and body-control modules where an EOL chip can strand millions of in-service vehicles. AEC-Q100-grade replacements on request.

Energy & Utilities

Grid control, metering, and substation equipment designed to run for 30 years. We extend that lifespan without touching the certified hardware.

Legacy & Service Programs

Aftermarket parts support, field-service kits, and last-time-buy mitigation for products no longer in active production.

Tell us which chip is
keeping you up at night.

Give us a part number and a production volume. We'll tell you if we can save your board — usually within a week.

Start Intake →
/ 07 — Request Quote

Let's keep your line running.

Send us the details of your EOL part and we'll come back with a feasibility assessment, timeline, and engineering fee. No obligation; no boilerplate.

Typical Turn
5 days / quote — 6-8 wks / prototype
NDA
Mutual NDA executed on request, prior to intake